ABSTRACT A nondestructive quality evaluation and control procedure for large-area, (001)-cut PZN-8%PT wafers is described. The crystals were grown by the flux technique engineered to promote (001) layer growth of the crystals. The wafers were sliced parallel to the (001) layer growth plane. Curie temperature (Tc) variations, measured with matching arrays of dot electrodes (of 5.0 mm in center-to-center spacing), were found to be better than ±4.0°C both within wafers and from wafer to wafer. After selective dicing to give final wafers of narrower Tc distributions (e.g., ±3.0°C or better), the wafers were coated with complete electrodes and poled at room temperature at 0.7--0.9 kV/mm. Typical overall properties of the poled wafers were: KT3=5,200 (±10% from wafer to wafer), tanδ<0.01 (all wafers), and kt=0.55 (±5%) (all percentage variations are in relative percentages). Then, the distributions of KS3, tanδ, and kt were measured by the array dot electrode technique. The variations in KS3 (hence KT3) and kt within individual wafers were found to be within ±10% and ±5%, respectively. The dielectric loss values, measured at 1 kHz, were consistently low, being <0.01 throughout the wafers. The kt values determined by the dot electrodes were found to be about 5% smaller than those obtained with the complete electrodes, which can be attributed to an increase in capacitance ratio due to the partial electroding. The k33 values, deduced using the relation KS3≈ (1-k233)KT3, from the mean KS3 and overall KT3 values, average 0.94 (±2%). The present work shows that the distribution of Tc within wafers can be used as a convenient check for the uniformity in composition and electromechanical properties of PZN-8%PT single crystal wafers. Our results show that, to control Δ KT3 and Δ kt within individual wafer to ≤ 10% and 5%, respectively, the variation in Tc within the wafer should be kept within ±3.0°C or better.
© 2003, by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.